Portable selective call receivers, such as pagers, typically use synthesizers including two or more PLLs (phase locked loops) for synthesizing frequencies necessary for the operation of a radio receiver included in the pager. In many applications, each PLL operates from a common clock source. Additionally, typically each PLL includes a set of digital frequency dividers used for controlling the programmable frequency of each PLL. In the case of a synthesizer including multiple PLLs, the frequency dividers of each PLL periodically reset at simultaneous intervals. The event of simultaneous reset of the frequency dividers causes each PLL to draw high levels of surge currents (e.g., 1-20 mA) from the power supply pins of the integrated circuit (IC) chip carrying the synthesizer. This high surge current in turn causes a voltage drop on the internal power supply traces of the IC, which in turn causes a modulation of the controlled oscillator of each PLL. This periodic distortion of the controlled oscillator causes the radio receiver of the pager to malfunction, thereby degrading the performance of the pager to receive messages, and under certain circumstances, rendering the pager inoperable.
FIGS. 1-3 show electrical block diagrams of prior art synthesizers with multiple phase locked loops (PLLs). FIG. 1 illustrates two PLLs 170-172 coupled to a power supply 174 by way of an external pin 176 of an IC. Also shown in FIG. 1, are the parasitic circuit elements generally associated with the layout of a circuit. Particularly, the parasitics consist of a network of inductances 174 and capacitances 176 some of which are internal to the synthesizer IC, and others which are caused by the layout of a PCB (printed circuit board). When a high surge current is experienced at the power supply lines 180 of the PLLs 170-172, the parasitics just described cause voltage drops that modulate the controlled oscillator of each of the PLLs 170-172. This distortion, as noted earlier, causes the controlled oscillators of each PLL 170-172 to generate distorted references frequencies, thereby causing the radio receiver of the pager to malfunction.
FIGS. 2-3 illustrate alternative embodiments used by prior art selective call receivers to resolve this problem. To minimize parasitic inductance, FIG. 2 illustrates a prior art method whereby the width of circuit traces internal and external to the IC are widened. Although this method helps to reduce voltage drops caused by surge currents on the power supply lines, it is disadvantageous in that it consumes a significant part of real-estate in the synthesizer IC, thereby increasing cost and reducing the amount of room available for other circuits. To further reduce distortion on the power supply lines, FIG. 3 illustrates an embodiment which builds on the embodiment depicted in FIG. 2. In this embodiment, each PLL 170-172 is designed to draw power from two or more supply pins, thereby reducing the amount of current drawn on the parasitic networks 182-184 of each pin and, consequently, minimizing modulation of the controlled oscillator of each of the PLLs 170-172. As was the case earlier, this method is costly and consumes even more real-estate than the embodiment of FIG. 2.
Accordingly, what is needed is a phase lock loop architecture that overcomes the foregoing disadvantages described in the prior art.